Digital IncrEncoder 1vXX

Functionality

• Connects one incremental encoder to FPGA

• Provides isolated 5V supply to encoder

• Reads differential signals from encoder

• Program CPLDs with firmware, see Programming the CPLD for details

Known issues

none

Compatibility

• Slots D1 to D5 can be used without limitations, D5 is suggested

Pinout

Pin	D-Sub 9	FPGA	Kubrich Encoder
0+	3	Dig_IO_12	blue
0-	4		red
A+	8	Dig_IO_13	green
A-	7		yellow
B+	5	Dig_IO_14	grey
B-	9		pink
Vcc	2		brown
GND	1		white

See also

• Schematic 1v00

• Programming the CPLD

Designed by

Eyke Liegmann (TUM) in 08/2019